Computer Architecture: I need to Implement a flexible cache simulator

Project Description:

In this project, you need to implement a simple cache simulator that takes as an input the
configurations of the cache to simulate, such as: size, associativity and replacement policy. When
you run you simulator, you need to additionally provide the path of the
trace file that includes the
memory accesses.
Your simulator will parse the trace file, which looks like:
R 0x2356257
W 0x257777
Each line consists of two parts, the operation type (read or write) and
byte address in hexadecimal.
After reading each line, the simulator will simulate the impact of that access on the cache state,
e.g., the LRU state of the accessed set and the current valid blocks in the set. Your simulator needs
to maintain information such as hits, misses and other useful statistics throughout the whole run.
In this project, you need to implement two different cache replacement policies: LRU and FIFO.
In LRU, the least-recently-used element gets evicted, whereas in FIFO, the element that was
inserted the earliest gets evicted.
Implementation hint: allocate your cache as a 2D array, where each row is a set. On each item of
the array keep track of information like the tag of the data in this block. You can create multiple
instances of such a 2D array for different purposes; for example, you can create another 2D array
to track the LRU position of the corresponding block in the LRU stack of the set.

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